1. Field of the Invention
The present invention relates in general to integrated circuit (IC) testers and in particular to an integrated circuit tester employing timing circuits having format sensitive timing calibration.
2. Description of Related Art
A typical per-pin integrated circuit tester includes a pattern generator and a set of tester channels, one for each pin of an integrated circuit device under test (DUT). The tester organizes each test into a set of successive test cycles, and during each test cycle each channel may initiate one or more test events at a corresponding DUT pin. A test event may be, for example, a change in state of a test signal supplied to the DUT terminal or the sampling of a DUT output signal at the terminal to determine whether the DUT output signal is behaving as expected.
The tester includes a pattern generator for supplying "format set" (FSET) data, "time set" (TSET) data and reference data (PG) to each tester channel for each test cycle. The FSET data and PG data together refer to a particular drive or compare format the channel is to use during the test cycle. The term "drive format" refers to the manner in which the channel controls the states of a test signal it may supply to the DUT terminal during the test cycle. The term "compare format" refers to the manner in which the channel samples and compares a DUT output signal to determine whether the DUT output signal is behaving as expected during the test cycle. The TSET data indicates times during a cycle at which events are to occur. The reference data PG can be used in conjunction with the FSET data to reference a particular drive format. When the FSET data specifies a compare format, the PG data typically indicates expected states of the DUT output signal. Each channel carrying out a compare format produces a "FAIL" signal when the DUT output signal it monitors does not match its expected state.
A typical tester channel includes a pin electronics circuit for generating a test signal at the DUT in response to a set of drive control signals indicating the test signal state (e.g., high, low or tristate). The pin electronics circuit also monitors any DUT output signal produced at the terminal and produces compare high (CH) and compare low (CL) signals indicating whether the DUT output signal is currently above a specified high logic level or below a specified low logic level. In addition to a pin electronics circuit, each tester channel also includes one or more timing signal generators and a formatter circuit. Each timing signal generator receives the TSET data from the pattern generator at the start of each test cycle and produces a timing signal pulse input to the formatter circuit with a delay following the start of the test cycle controlled by the TSET data. The formatter circuit receives the FSET and PG data from the pattern generator, the timing signals produced by the timing signal generators and the CH and CL signals from the pin electronics circuit and produces the control signal inputs to the pin electronics circuit and the output FAIL signal. The FSET and PG data indicate the drive or compare format to be carried out during a test cycle and also indicate which timing signals are to control the timing of events within the indicated format.
In order for a test to be successful, the timing of test events at the various DUT terminals must be precisely coordinated. The timing signal generators of all tester channels use the same master clock signal as a timing reference so that they can coordinate the timing of their output timing signals. However a number of factors introduce errors into their timing coordination. For example, since the tester channels are distributed in space, the master clock signal may not arrive concurrently at the various timing signal generators. Also signals paths between the tester channels and the DUT terminals they access may vary in distance. Thus a test signal from one channel may take longer to reach a DUT terminal than another, or one DUT output signal may take longer to reach a tester channel than another. Moreover, while the tester channels are typically of similar construction, process and temperature variation between the integrated circuit devices forming the separate tester channels can cause differences in the amount of time they require to actually make a test event happen in response to a timing signal.
To reduce these timing differences between channels, each timing signal generator is typically provided with a separate programmable delay circuit for adjustably delaying its output timing signal. The amount of delay provided by the delay circuit is controlled by calibration data stored in a register. To calibrate the tester, all of the tester channels may, for example, be connected to terminals of a device such as an oscilloscope that can measure timing differences between signals applied to its terminals. The tester is then programmed so that all tester channels are expected to produce output test signals concurrently. If the oscilloscope shows that the test signal produced by any one channel lags or leads the others, the calibration data in the control register for the delay circuit of the timing signal generator that triggered the lagging or leading test signal is adjusted accordingly. Thus channel-to-channel variation in the delay between timing signal generation and test signal state change is substantially eliminated.
One of the heretofore unresolved problems associated with timing calibration has been that the delay between timing signal generation and test event varies not only from channel-to-channel but from event format-to-format. For example, in one drive format a test signal is driven high in response to a timing signal while in another drive format the test signal is driven low in response to the test signal. Each event format requires the timing signal to travel a separate path through the tester channel on its way to triggering the state change event because each state change event is implemented by a separate set of logic devices within the tester channel. Since each kind of event requires the timing signal to follow a different signal path, and since different signal paths have differing inherent delays, the delay between a timing signal and the event it triggers depends on the nature of the event being triggered.
Drive and compare formats have markedly differing timing requirements. For drive formats, a timing signal that is to trigger a change in state of a test signal at some time specified by the TSET data should lead the specified time by an appropriate amount to account for the inherent delay between the timing signal generator and the DUT terminal. On the other hand, if a channel is to sample and compare a DUT output signal to determine its state at the specified time, the sample and compare operation should be carried out some time after the specified time to account for the time the DUT output signal requires to travel to a sampling circuit within the channel. Therefore the timing signal that triggers a compare event should be produced later than a timing signal that triggers a drive event relative to the time specified by the TSET data.
Thus when timing delay is calibrated to provide a standardized signal path delay for one kind of event format, that timing calibration may not be accurate when the channel subsequently carries out another kind of event format. Some improvement to this timing problem has be achieved by determining the value of calibration data needed to optimize timing for a variety of test formats and then averaging the results to produce the timing calibration data values actually used. This procedure minimizes the maximum possible timing error for any one kind of event format. Nonetheless format sensitive timing calibration errors remain and these errors limit the tester's timing resolution. As integrated circuit speed continues to increase, we must improve the timing resolution of the machines that test them. Thus small format sensitive timing calibration errors must be made smaller.